1. Field of the Invention
The present invention relates to an output buffer circuit of a semiconductor integrated circuit of CMOS (complementary metal oxide semiconductor) construction such as a gate array or standard cell, and more particularly to an output buffer circuit for outputting a digital signal of relatively high frequency and transmitting such a digital signal to another semiconductor integrated circuit. The present invention further relates to a transmitter using this output buffer circuit.
2. Description of the Related Art
In semiconductor integrated circuits of CMOS construction, many techniques have been proposed for transmitting digital signals of relatively high frequency by reducing signal amplitude to below normal CMOS levels.
As an example, Japanese Patent Laid-open No. 225275/92 describes transmission using GTL (a coined descriptor) drivers and receivers. Such a GTL driver takes the form of an open-drain driver using an N-channel MOS transistor at the output stage, the transmission line adopting a circuit construction employing terminating resistors to pull up the transmission line potential to that of the terminal power supply.
However, the above-described prior art has the drawback that the rise time of the output waveform is longer than the fall time in cases in which the transmission line has a large capacitance component.
In addition, output impedance is relatively low when the output is at a low level because the N-channel MOS transistor of the output stage is in a conductive (ON) state, but output impedance becomes extremely high when the output is at a high level because the N-channel MOS transistor enters a non-conductive (OFF) state. Consequently, there is the problem that when a transmission line is long, matching between the transmission line and output impedance is difficult to achieve and reflected noise increases significantly, thereby preventing stable high-frequency signal transmission.